ILP and Iterative LP Solutions for Peak and Average Power Optimization in HLS

In this paper, we tackle the problem of peak and average power optimization in high-level synthesis. Because of the quadratic relationship of supply-voltage to the dynamic power consumption, voltage scaling is considered as the most efficient technique for reducing power consumptions in CMOS circuits. We present an MILP formulation for the scheduling problem using multiple supply-voltages in order to optimize peak power as well as average power and energy consumptions. As the design problem becomes large, exact solution takes a tremendous amount of run-time; and to explore the design space in a reasonable amount of time, a high quality heuristic is needed. Thus, we devise a two-phase heuristic to solve the multiple supply-voltages scheduling for peak and average power minimization. In the first phase, a guided LP relaxation is developed. Following the relaxed LP schedule, a power-area-saving procedure is developed. Results for peak and average power of our two-phase heuristic well match those obtained by the optimal solution as has been validated through extensive experiments on several benchmarks.